Technical Discussion

ARM7TDMI
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->The ARM7TDMI is memeber of the advanced RISC MAchines ( ARM) family of general purpose 32 bit microprocessor.
->offers hifh performance for very low power consumption and price.
->It architecture is based on reduced instruciton set computer( RISC)
what is difference between RISC and CISC?
RISC->Reduced instrution set computer
CISC->Complex instrution set computer

Complex instructions came about in order to maximize the performance of early computers. At that time, computers executed instructions sequentially. The first instruction had to complete the execution cycle before the next instruction could begin. Designers combined sequences of instructions into single instructions. This reduced the amount of time spent retrieving instructions from memory , although these instructions did require multiple clocks cycles to execute.


RISC architecture makes use of a small set of simplified instructions in attempt to improve performance . These instructions consist mostly of register-to-register operations . Only load and store instructions access memory . Since almost all instructions make use of
register addressing, there are only a few addressing modes in a reduced instruction set computer and there are a large number of general-purpose registers .
RISC instructions complete execution in one machine cycle using pipelining technique.

->Pipelining is the technique allows the next instruction to enter the execution cycle while the previous instruction is still processing .
i.e when when one instrution is being executed ,its successor is being decoded and a third instrution is being fetched from memory.
->ARM7TDMI is a 3 stage pipeline 32 bit RISC processor.
->The processor is characterized by single data and adress bus for instructions and data.

Processor operation states:
The CPU have two instruction sets
1.ARM instruction set -> 32 bit wide instructions n provided max performance
2.Thumb instruction set -> 16 bit wide n provide max code density.instructin operate on 8,15,32 bit data types.

The THUMB Concept:
ARM7TDMI employes a unique architectural stragey known as THUMB which is suited for application where memory is issue or code density is issue.
THUMB followed super reduced instruction set.it sets 16 bit instrution lenght allows it to approach twice the density of standard arm code at the same time

retaining most of the ARM's advantage over a traditional 16 bit processor .
Thumb operated on the same 32 bit register set as ARM code.
Each 16 bit Thumb instruction has a corresponding 32 bit ARMinstruction with the same effect on the processor model.

ADV of ARM instruction
To manupulate 32 bit integers with single instructions and to address a large address space effectively.

ADV of Thumb
Abitlity to swictch back to full ARM code and execute at full speed.critical loops like
-fast interrups
-DSP algorithms can be coded using the full ARM instrution and linked with THUMB.


Switching state:
-> 1.Entering into THUMB state can be achieved by executing a BX intruction with the state bit (bit 0) set in the operand register.
2.Transition to thumb state will also occur automatically on return from an exception like IRQ,FIQ,UNDEF,ABORT,SWI if the exception was entered with the processor in THUMB state.

->Entering ARM stage can be achieved on execution of the BX instruction with the state bit clear in the operand register.
2.On the processor taking an exception like ( IRQ,UNDEF,FIQ,ABORT,SWI,RESET)

Memory format:
ARM7TDMI views memory as linear collection of bytes numbered upward from 0. bytes 0 - 3 hold the first stored word.
ARM7TDMI treat words in memory in two ways
1.BIG Endian-> MSB is at lowest address, word is addressed by the byte address of MSB
2.Little Endian.->LSB is at lowest address,word is addressed by the byte address of LSB.


Operating modes:
ARMTDMI supports seven modes of operation
1.USER ( usr )-> The normal ARM program execution
2.FIQ ( fiq) -> Designed to support a data transfer of channel process.
3.IRQ( irq) ->Used for general purpose interrupt handling.
4.Supervisor( svc)-> Protected mode for the operating system.
5.Abort mode(abt) ->Entered after a data or instruction prefetch abort.
6.System (sys) ->A previlaged user mode for the operating system
7.Undefined (und) ->Entered when an undefined instrution is executed.

Mode changes is under software control , or by external interrupt or exceptions.
In order to service interrupts or exception or to access protected resource the cpu entered non user moders know as previleged modes.

Registers->Total 37 registers - 31 GPIO 32 bit and 6 status registers.